1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor integrated circuit packages and, more particularly, to burn-in and testing of chips prior to packaging, especially multi-level modular packaging.
2. Description of the Prior Art
The many and complex steps for formation of integrated circuits on semiconductor wafers which are later diced into chips or dies assures that manufacturing yield of the chips or dies will seldom be 100% even though the technology has become quite sophisticated and process conditions and tolerances can be much better controlled and regulated than in the very recent past. However, each process step or group of process steps carries a cost and it would be desirable to remove defective chips from the process at as early a point in the manufacturing process as possible.
On the other hand, testing and inspection during relatively early stages of manufacture is, itself, costly and the cost of individual testing and inspection procedures diminishes somewhat as the chip package becomes more complete. Cost of testing also increases with thoroughness of testing at any stage of production and at early stages in particular since more thorough testing generally requires more connections to be made to the chip and exercised during testing while structures for making convenient and reliable connections to the chip have generally not been formed. Thus, increasing the number or thoroughness of test procedures early in the manufacturing process rapidly produces diminishing returns and a trade-off remains between the expense of further processing of chips beyond the point at which a defect is created (or could potentially be detected) and the cost of more thorough and frequent testing at early stages of production. Even if optimized, the cost of further processing of defective chips and reduced manufacturing yield based on tests which are, in fact, performed is a significant portion of the cost of manufacturing integrated circuits.
Of course, over small batches of chips or wafers, small process variations beyond the available level of process parameter regulation causes variation in manufacturing yield which prevents quantitative optimization of the number, thoroughness and points during manufacture of the tests conducted. Generally, a testing strategy is assumed and its effectiveness evaluated over a number of batches of completed chip packages to refine the strategy in view of the types of defects later discovered to reduce or compromise manufacturing yield. This approach has led to a strategy in which, for single chip packages, only screening for catastrophic defects is done at various points during manufacture before the chip package is completed.
In recent years, however, performance enhancements and manufacturing economies have led to the design of so-called multi-layer modular (MLM) packaging of integrated circuits in which a single package includes a potentially unlimited plurality of chips (which may be formed by incompatible technologies) and complex circuitry to interconnect the chips formed on surfaces of and vias in lamina which are later bonded together to form the MLM.
While some rework of these modular packages is possible, including replacement of chips therein which are later found to be defective, such rework carries its own costs and process complexities. Further, even if the manufacturing yields of individual chips is high, the number of chips included in the package will increase the likelihood that one or more chips must be replaced in any given module. Rework, itself, can cause chip damage or other damage such as solder voiding for the replaced chip which would require a further rework procedure. For this reason, the concept of the "known good die" (KGD) could potentially produce reduction of overall manufacturing costs of advanced integrated circuit packages by potentially avoiding processing or rework costs with full functional testing prior to package completion.
Another complexity is presented by the fact that some change in manufacturing yield will occur during an initial period of operation of an integrated circuit. That is, a definition of a "known good die" which is based on whether or not it functions correctly the first time it is operated may not be sufficient to obtain the potential benefits of avoiding rework. Completed packages are generally subjected to a "burn-in" period of operation and further testing to determine actual operating characteristics and to project whether or not the package will remain reliably functional and within operating margins. It appears that rework can only be avoided in a sufficient number of cases to be economically favorable if burn-in and full functional testing are performed to determine a "known good die" prior to completion of the integrated circuit package.
Some efforts toward burn-in and testing of chips prior to package assembly have been attempted in designs using lead frames to mount and form connections to a chip. However, in MLMs, a so-called "flip-chip" mounting arrangement is much preferred. "Flip-chip" mounting involves the attachment of solder bumps or preforms such as so-called C4 (controlled collapse chip connections) preforms to connection pads on a major surface of the chip and then inverting the chip and attached preforms for mounting to a mirror-image array of connection pads of a substrate (e.g. another chip, MLM, carrier, board or the like) by heat treatment that forms reliable solder connections between the substrate and chip. To date, this structure has required solder attachment to a testing apparatus or compressional connection against pads to which the package would otherwise be soldered. In either case, some degree of deformation of the solder bumps or preforms inevitably occurs (possibly aggravated by high chip temperature during burn-in operation and/or testing) and solder voids and other connection defects generally result due to such deformations when the chip is later assembled with and soldered to a package structure.
Additionally, it is customary to make temporary connections to chips through use of a so-called ball grid array (BGA) chip carrier. A BGA is a substrate having plated areas on both sides thereof. Plated areas on one side are arrayed for attachment of a chip by soldering, compression and/or other arrangements. Plated areas on the other side are provided for the attachment of contact balls to make temporary contacts or to be soldered to a testing and/or burn-in apparatus. Connections between plated areas of opposite sides of the BGA are connected by plated through-holes (PTH).
For flip-chips having solder bumps or solder preforms (hereinafter sometimes collectively referred to as "protrusions"), the through holes serve to receive the bumps or preforms along the annular edge of the PTH for a relatively reliable connection under compression. However, the reduced contact area along such an annulus may aggravate deformation of the solder bumps or preforms. More economically significant, however, is the fact that BGAs are very high precision components which are very expensive and yet very subject to wear and damage and generally have a short useable lifetime.
To date, no alternatives to soldering or compressional connection have been proposed which accommodate the extremely close spacing of contact pads on flip-chip style chips while supporting the extended duration of connections required for burn-in operation and full functional testing. Similarly no arrangements for extending the usable life of ball grid arrays while providing connections to flip-chips have been proposed.